In computer systems it is conventional to define in each instruction to be executed a set of register addresses which are used to access a register file in the computer system. The register addresses usually include first and second register addresses defining registers from which operands are extracted and at least one destination register address defining a register into which the results of an operation are loaded. Data processing instructions generally use the contents of the first and second registers in some defined mathematical or logical manipulation and load the results of that manipulation into the defined destination register. Memory access instructions use the register addresses to define memory locations for loading and storing data to and from a data memory. In a load instruction, source registers define a memory location from which data is to be loaded into the destination register. In a store instruction, the source registers define a memory location into which data is to be stored from the destination register.
Some computer systems have more than one execution channel. In such computer systems, each execution channel has a number of functional units which can operate independently, whereas both execution channels can be in use simultaneously. In some cases the execution channels share a common register file. It is useful in such architectures to provide instructions which simultaneously instruct both execution channels to implement a function so as to speed up operation of the processor. In such a scenario, a so-called long instruction may have two instruction portions each intended for a particular execution channel. Each instruction portion needs to define the register addresses for use in the function to be performed by the execution channel for which it is intended. In some cases both instruction portions may wish to define associated or the same register addresses. In these situations a long instruction needs to define two sets of register addresses, one for each execution channel.
In such known computer systems with more than one execution channel, parallelism has been specified implicitly, for example with a sequence of instructions whose parallelism is extracted at run time in a superscalar architecture, or explicitly with wide instructions, e.g. long instruction words (LIW) or very long instruction words (VLIW) which are architecturally defined to execute a set of separate components together. These known methods have the backlash in common that they require a lot of instruction space.
It is an aim of the present invention to reduce the number of bits required in an instruction for accessing a register file, in particular in the context of multiple execution channels in a computer system. As another object of the present invention in case of a repeated execution of an operation the number of the respective instruction shall be reduced. These and other objects will become apparent in the detailed description of the invention and the drawings.